DFT Engineer

Job Title: DFT / Design for Test Engineer (Lead / Principal / Architect)

Experience: 3 to 18 Years

Location: Bangalore, India (Onsite)

Notice Period: Immediate to 90 Days (Candidates currently serving notice period are highly preferred)

About the Role

We are looking for deeply passionate, technically rigorous DFT Engineers across multiple experience levels to join our elite engineering group in Bangalore. Whether you are a rising star with 3+ years of execution experience or an industry veteran/architect with up to 18 years of experience, we want individuals who don't just execute scripts, but possess a deep architectural understanding of the why behind test methodologies.

This is a long-term career opportunity for professionals who are genuinely driven to learn, grow, and establish themselves among the top-tier DFT experts in the Indian semiconductor market.

Key Responsibilities

• Architect, design, and implement DFT strategies for complex, high-performance SoCs and AI accelerators.
• Take complete ownership of tool flows, scripting, and debug constraints for assigned DFT domains.
• Collaborate closely with RTL design, synthesis, and post-silicon validation teams to ensure seamlessly integrated test structures.
• For Senior/Lead roles: Mentor junior engineers, drive DFT architecture definition, and lead chip-level test closure.

Required Technical Expertise (Any one or multiple techniques)

We are looking for solid, fundamental mastery in any one or a combination of the following techniques and flows:

• Scan & ATPG: Classic Scan insertion, Compression methodologies, and complex ATPG (Stuck-at, Transition, At-Speed, Cell-Aware).
• Memory BIST (MBIST): Industry-standard MBIST insertion, repair algorithms, and integration.
• Logic BIST (LBIST): In-system test architectures, especially crucial for automotive or high-reliability chips.
• Boundary Scan (BSCAN): Classic IEEE 1149.1 JTAG architecture, implementation, and board-level test support.
• IJTAG: Deep understanding of IEEE 1687 infrastructure, instrument integration, and pattern retargeting.

The Plus Factors (Highly Valued)

• Hands-on experience with SSN (Streaming Scan Network).
• Direct experience handling AI / Machine Learning Chip architectures.
• Advanced multi-die/chiplet test standard experience.

Core Candidate Requirements

• Deep Architecture Understanding: You must possess a strong, bottom-up conceptual understanding of the techniques you have worked on. You should be able to explain the underlying logic, tool command behavior, and structural debug choices deeply.
• Exceptional Logical & Communication Skills: Strong problem-solving capabilities with the ability to articulate complex technical challenges and solutions clearly to stakeholders.
• Tool Flow Proficiency: Mastery over major industry-standard toolchains (Synopsys TestMax/DFTMAX/TetraMAX, Siemens Tessent suite, or Cadence Modus).
• Genuine Passion: We are looking for engineers who are genuinely fascinated by the VLSI test domain and want to master it for the long term.

Why Apply?

• Work on cutting-edge, complex silicon architectures.
• Collaborative environment prioritizing technical excellence over bureaucratic process.
• Direct path to becoming an industry-recognized DFT expert in India.

How to Apply:

Genuine and passionate candidates only. If you match the location requirement (Bangalore) and are ready to tackle deep technical challenges, please submit your updated resume highlighting your specific domain expertise (e.g., Scan/ATPG, MBIST, JTAG, SSN) and your current notice period status.

Email - [email protected]